Since all the benchmark is in 2D distribution, we segregate sinks according to their density and nearest neighbour position. Our contributions in this work are as followsįirst, we place the sinks in different stacks according to their positions. A trade-off is also made between wire length and minimisation of number of TSV insertion to minimise dynamic power consumption. Segregation method followed by bottom-up iterative routing approach helps in minimising of wire delay and dynamic power. Then using segregation method, routing is done with inserting buffers and TSVs. Our clock tree generation method primarily focused to minimise wire length by grouping the closer clock sinks placed on different dies. We formulate the problem as optimisation problem with minimisation of multiple parameters, like wire length, TSV count, number of buffers, delay and dynamic power consumption to be minimised. We minimise TSV count for better performance (lower power consumption, lower skew, lower delay) with respect to area overhead. This routing method is quite new in the context of 3D ICs. Our segregation method is based on the quad tree structure and recursive process to route the clock to the sinks in 3D IC. Single TSV insertion may lead to increase wire length as well as skew and dynamic power consumption. In our proposed method, we consider multiple TSVs insertions. So, we carefully design our proposed algorithm to reduce the TSVs count. In 3D IC clock, TSV insertion may induce side effects in the current design and manufacturing process, such as thermal problem, mechanical stress and TSV noise coupling etc. The clock tree is constructed to avoid existing obstacles on the chip. So, we are interested in designing a highly balanced, low-power clock tree for 3D ICs to optimise skew and power consumption. Vital tree parameters such as skew and dynamic power consumption are also of great importance. On the other hand, scaling and blockages reduce routing area. Its power consumption can take up to 70% of the chip's total dynamic power ]. It is a major contributor to the chip's power in high-performance VLSI circuits. The clock tree is one of the largest and most frequently switched networks in an IC. So, optimising the number of TSVs is also important.ģD IC clock routing with obstacle avoidance TSV plays a major role in enhancing the performance of the 3D clock network, , ], like minimising delay and power. In 3D IC, clock tree network distributes throughout all the stacks and connects all clock sinks in different layers using TSVs as shown in Fig. The TSVs are used to provide clock signals to all the dies stacked vertically. A great amount of chip-power dissipation takes place throughout the clock network. The clock routing network drives higher load capacitance. Also, to avoid propagation delay violations, the clock network latency must be as low as possible. In our proposed work, the main focus is on controlling clock skew and power consumption for 3D IC. Thus, minimised interconnect wire length further contributes to great save on delay, power, area and cost ]. Interconnect wire length can be reduced significantly by 3D stacking. This Z direction interconnect is termed as TSV. For 3D IC, clock signal distributes not only through X and Y direction but also Z direction interconnected. In 2D IC, clock signal distributes to only X and Y direction. 3D IC basically consists of a number of dies stacked on top of each other, where the inter-die connection is obtained with the use of through-silicon-via (TSV) ]. Multiple approaches are being followed for stacking purposes on 3D ICs, such as (i) die to die, (ii) die to wafer and (iii) wafer to wafer. This technology reduces the footprint of a die while increasing the number of transistors per chip. This design gives us a way to move beyond Moore's law. Hence, it is essential to move into the third dimension for IC design. The other issue is the physical limitation which has an effect on technology scaling. Further scaling may cause unavoidable physical limitations. As the number of transistors is increased, clock routing has become too complex and power consumption per unit area has increased excessively ]. Aggressive technology scaling has increased transistor number per IC to a billion. Moore's law states that the number of transistors in an IC doubles approximately every two years ]. This growth has largely followed Moore's law. The electronics industries have enjoyed remarkable growth and innovations over the past decades, ].
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